RT9730 1 ds9730-01 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. charging system safety device general description the RT9730 is an integrated circuit (ic) designed to replace passive device in charging system with extra protection function. it is optimized to protect low voltage system from up to 28v high voltage input. the ic monitors the input voltage to make sure all parameters are operating in normal range. it also monitors its own temperature and turns off the mosfet when the chip temperature exceeds 140 c. when the input voltage exceeds the threshold, the ic turns off the power mosfet within 1 s to remove the power before any damage occurs. user can monitor the adapter input voltage from the chrin pin, which has 50ma current capability. the gate of the p-mosfet will be controlled by the external charging controller from gatdrv pin if all parameters are operating in normal range. the RT9730 is available in a wdfn-8l 2x2 tiny package to achieve best solution for pcb space and total bom cost saving considerations. features z z z z z no external blocking diode requiring z z z z z over voltage turn off time of less than 1 s z z z z z high accuracy protection thresholds z z z z z over temperature protection z z z z z high immunity of false triggering under transients z z z z z thermal enhanced 8-lead wdfn package z z z z z rohs compliant and halogen free applications z cellular phones z digital cameras z pdas and smart phones z portable instruments pin configurations (top view) wdfn-8l 2x2 acin acin out out chrin gnd nc 7 6 5 1 2 3 4 8 gnd 9 gatdrv typical application circuit RT9730 acin gnd chrin out gatdrv 1f 0.2 soc chrin gatedrv out vbat battery c out 1f v in c in 1f jf=w marking information jf= : product code w : date code RT9730 package type qw : wdfn-8l 2x2 (w-type) lead plating system g : green (halogen free and pb free)
RT9730 2 ds9730-01 april 2011 www.richtek.com function block diagram functional pin description pin no. pin name pin function 1, 2 acin input power source pin. it can withstand up to 30v input. 3, 9 (exposed pad) gnd analog ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.. 4 nc no internal connection. 5 gatdrv external control pin for controlling the p-mosfet by charging controller. 6 chrin voltage is equal to vin as vin in power good range and providing ? 25ma for system at most. 7, 8 out connect to out resistor and out pin of charging controller. control logic mux sw sw inovp uvlo otp acin out chrin gnd gatdrv
RT9730 3 ds9730-01 april 2011 www.richtek.com electrical characteristics recommended operating conditions (note 4) z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v in ------------------------------------------------------------------------------------------------ ? 0.3v to 30v z output (as v in > v out , normal mode) --------------------------------------------------------------------------------- ? 0.3v to 7v z output (as slee p mode) -------------------------------------------------------------------------------------------------- ? 0.3v to 4.5v z other pins ------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wdfn-8l 2x2 -------------------------------------------------------------------------------------------------------------- 0.833w z package thermal resistance (note 2) wdfn-8l 2x2, ja --------------------------------------------------------------------------------------------------------- 120 c/w wdfn-8l 2x2, jc -------------------------------------------------------------------------------------------------------- 8.2 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v (v in = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit vin under voltage lockout threshold v uvlo v in rising 2.5 2.7 2.9 v vin under voltage lockout hysteresis v uv lo -- 100 -- mv vin bias current when enable -- 200 600 a reverse leakage i leakage as acin floating -- 5 10 a operation voltage 4.3 -- 6.5 v operation current -- -- 1 a protections input ovp reference voltage v inovp 6 6.25 6.5 v input ovp h ysteresis -- 60 100 mv input ovp propagation delay -- -- 1 s otp rising thershold -- 140 -- c otp hysteresis -- 20 -- c power mosfet r ds(on) between acin to out r ds(on)_out measure @ 500ma. 4.3v < v in < 6v -- -- 500 m r ds(on) between acin to chrin r ds(o n)_chrin measure @ 50ma. 4.3v < v in < 6v -- -- 3
RT9730 4 ds9730-01 april 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT9730 5 ds9730-01 april 2011 www.richtek.com typical operating characteristics supply current vs. temperature 0 20 40 60 80 100 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature supply current ( a) acin = 5v, out = open, chrin = open, gatdrv = 5v ( c) r ds(on) vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature r ds(on) (ohm) acin = 5v, out = 500ma, chrin = open, gatdrv = 0v ( c) ( ) chrin r ds(on) vs. temperature 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature r ds(on) (ohm) acin = 5v, out = open, chrin = 50ma, gatdrv = 5v ( c) ( ) out r ds(on) vs. input voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.7 3.1 3.5 3.9 4.3 4.7 input voltage (v) r ds(on) (ohm) acin = 5v, out = 500ma, chrin = open, gatdrv = 0v ( ) out current vs. gatdrv voltage 0 50 100 150 200 250 300 350 400 450 500 2.5 2.7 2.9 3.1 3.3 3.5 3.7 gatdrv voltage (v) out current (ma) acin = 4.5v, r load = 9.1 chrin r ds(on) vs. input voltage 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2.73.13.53.94.34.7 input voltage (v) r ds(on) (ohm) acin = 5v, out = open, chrin = 50ma, gatdrv = 5v ( )
RT9730 6 ds9730-01 april 2011 www.richtek.com ovp vs. temperature 5.00 5.25 5.50 5.75 6.00 6.25 6.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ovp (v) acin = 5v, out = open, chrin = 1k , gatdrv = 5v ( c) input ovp propagation delay time (500ns/div) (1v/div) chrin = 1k , gatdrv = acin acin chrin input ovp recovery delay time (1 s/div) (1v/div) chrin = 1k , gatdrv = acin acin chrin
RT9730 7 ds9730-01 april 2011 www.richtek.com application information operation state the operation state is shown in the following figure 1. at power-off state, the RT9730 will check whether v in is > uvlo threshold. if v in is higher than the uvlo threshold, the RT9730 will check whether the junction temperature is over the otp threshold. if the junction temperature is higher than the otp threshold, the internal p-mosfet will be turned off. if the junction temperature is lower than the otp threshold, the RT9730 will check whether v in is higher than the ovp threshold or not, if v in is higher than the ovp threshold, the RT9730 will turn off the internal p- mosfet immediately within 1 s. if all of the checks including v in > uvlo, t j < otp and v in < ovp are ok, the ic will operate normally. figure 1. operation state diagram for ovp function input over voltage protection (ovp) the RT9730 monitors the input voltage to prevent abnormally high input voltage from causing output system failures. when the input voltage exceeds the threshold, the RT9730 will turn off the power mosfet within 1 s to prevent damage to the electronics in the handheld system. the hysteresis for the input ovp threshold is 100mv. when the input voltage returns to normal operation voltage range, the RT9730 re-enables the mosfet. the RT9730 can with stand an input voltage up to 30v without suffering damage. battery voltage monitor the RT9730 monitors the battery voltage by the out pin. when the battery voltage exceeds the voltage level of (v in ? 0.2v), the RT9730 will turn off the mosfet and the battery will not be charged. the RT9730 will recharge the battery when the battery voltage is lower than the voltage level of (v in ? 0.2v). internal over temperature protection (otp) the RT9730 monitors its own internal temperature to prevent thermal failures. when the internal temperature reaches 140 c with a built-in hysteresis of 20 c, the ic turns off the power mosfet. the ic does not resume operation until the internal temperature drops below 120 c. input under voltage protection (uvlo) the RT9730 monitors input voltage to prevent abnormally low input voltage from causing output system failures. the RT9730 input under voltage protection threshold is set to 2.7v. when the input voltage is under the threshold, the RT9730 will turn off the power mosfet within 1 s. when the input voltage returns to normal operation voltage range, the RT9730 re-enables the mosfet. system operation description figure 2 shows the connection of RT9730 in a system diagram. the out pin of the soc will sense the voltage of the 0.2 sense resistor and the voltage of the vbat pin. then, the gatdrv pin of the soc can control the mosfet of the RT9730 accordingly to determine the level of the charge current. the power of the soc is provided by the chrin pin of the RT9730. the RT9730 also provides ovp function to the soc. once the input voltage at the acin pin is higher than the ovp level, the RT9730 will shutdown to prevent the soc from damage. if the voltage of the battery connected to the vbat pin is full, the RT9730 stops charging by turning off the out pin. input and output capacitors of 1 f are recommended to be placed as close to the ic as possible. start v in > uvlo t j > otp v in > ovp y yy n n n power-off status otp status pfet=off ovp status p-mosfet = off(fast) normal status p-mosfet = on and control by gatdrv figure 2. application diagram of RT9730 with soc RT9730 acin gnd chrin out gatdrv v in c in c out 1f 1f 0.2 soc chrin gatedrv out vbat 1f battery
RT9730 8 ds9730-01 april 2011 www.richtek.com figure 3. derating curves for RT9730 packages layout consideration the RT9730 is a protection device. careful pcb layout is necessary. for best performance, place all peripheral components as close to the ic as possible. a short connection is highly recommended. the following guidelines should be strictly followed when designing a pcb layout for the RT9730. ` the exposed pad, gnd, must be soldered to a large ground plane for heat sinking and noise prevention. the through-hole vias located at the exposed pad is connected to the ground plane of internal layer. ` acin traces should be wide to minimize inductance and handle the high currents. the trace running from input to chip should be placed carefully and shielded strictly. ` the capacitors must be placed close to the part. the connection between pins and capacitor pads should be copper traces without any through-hole via connection. figure 4. pcb layout guide to battery to baseband gate controller input capacitor must be placed between gnd and acin to reduce noise. the capacitor must be placed between gnd and chrin to reduce noise. from adapter to baseband charger controller c in gnd acin acin out out chrin gnd nc 7 6 5 1 2 3 4 8 gnd 9 gatdrv the exposed pad and gnd should be connected to a strong ground plane for heat sinking and noise prevention. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT9730, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn- 8l 2x2 packages, the thermal resistance, ja , is 120 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (120 c/w) = 0.833w for wdfn-8l 2x2 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT9730 package, the derating curve in figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four-layer pcb
RT9730 9 ds9730-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension w-type 8l dfn 2x2 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.950 2.050 0.077 0.081 d2 1.000 1.250 0.039 0.049 e 1.950 2.050 0.077 0.081 e2 0.400 0.650 0.016 0.026 e 0.500 0.020 l 0.300 0.400 0.012 0.016 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
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